1. Field of the Invention
The present invention generally relates to a semiconductor memory device including an internal clock doubler, and more specifically, to a technology of holding output data for 2 clocks only when data are outputted in a read mode.
2. Description of the Prior Art
A random access memory (hereinafter, referred to as “RAM”) of semiconductor memories which can access randomly to a memory place and perform both write and read operations of information has been widely used in a memory device of computer and its peripheral terminal equipment.
The RAM includes a dynamic RAM for performing a refresh operation for each predetermined period not to delete information and a static RAM whose information is not deleted only if the static RAM is connected to power.
Although the static RAM is easily connected to other integrated circuits, the static RAM requires more than 3˜4 times devices if it is used with the same memory capacity as that of the dynamic RAM. As a result, the static RAM becomes more complicated and expensive.
Recently, studies have been made on a pseudo SRAM for performing the same operation as that of the static RAM using a cell of the dynamic RAM. In the pseudo SRAM, the chip size becomes smaller than that of the conventional static RAM, and high integration such as 16 Mbit, 32 Mbit and 64 Mbit can be embodied.
The pseudo SRAM outputs data with 1 clock hold or 2 clock holds. In the 1 clock hold, outputted data are maintained only for 1 clock, and other data are outputted if the next clock enters. In the 2 clock holds, outputted data are maintained for 2 clocks, and other data are outputted if the next clock enters. That is, during the 2 clock holds, if data are outputted in the first clock, the data are maintained until the second clock, and if other data are outputted in the third clock, the other data are maintained until the fourth clock.
In this way, the conventional semiconductor memory device uses an internal clock doubler in order to continuously maintain output data for 2 clocks.
However, the conventional semiconductor memory device holds data for 2 clocks in a read mode as well as in a write mode unnecessarily by using an internal clock doubler. As a result, the whole operation time of the chip increases.